This invention relates to a frequency synthesizer comprising a reference frequency generator, a frequency control circuit which includes a variable frequency reduction means having a cycle cancellation circuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said cancellation circuit from a pulse source, and a jitter compensation signal circuit connected to the frequency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency that would otherwise be caused by each cancelled cycle.
Such frequency synthesizers are known and are either of the "direct" type in which the output frequency is derived directly from the reference frequency or of the indirect, or phase lock loop, type in which the output frequency is generated by a variable frequency oscillator forming part of a phase lock loop which locks the oscillator to a predetermined rational fraction, which is to be understood as including a multiple, of the reference frequency.
Examples of direct frequency synthesizers are described in U.K. Patent Specification Nos. 1,545,953 and 2,062,315, and examples of phase lock loop synthesizers are described in U.K. Patent Specification Nos. 1,447,418 and 2,068,185A. In each type, it is known to include in the frequency reduction means a variable modulus divider to provide the major part of the required frequency reduction. Such dividers generally produce spectrally pure frequencies which are exact subharmonics of the frequency which is to be divided. The frequencies other than subharmonics are produced by a cycle cancellation technique in which selected cycles of the frequency to be reduced are cancelled. Such a technique is well known and is alternatively referred to as sidestep programming (see, for example, A. F. Evers and D. J. Martin, "Improved forms of digital frequency synthesizers", IEE Colloquium Digest 1972/11, pp. 9/1 to 9/5), pulse blanking, pulse removal, pulse cancellation, and pulse or cycle swallowing. The technique is also described in Mullard Technical Note 142 "Versatile LSI frequency synthesiser" pp. 8, 9.
For example, a frequency synthesizer may have a range of 1.6 MHz to 30 MHz adjustable by means of one or more modulo-N dividers where N is adjustable to provide the range in 1 kHz steps. These steps may then be further subdivided by the use of a rate, or fractional, multiplier which, for example, produces an output frequency variation of 0 to 990 Hz in 10 Hz fractional steps. In this manner, the whole range 1.6 MHz to 30 MHz is covered in 10 Hz fractional steps. The adjustable frequency given by these fractional steps is usually referred to as the offset frequency and is provided by means of a cycle cancellation circuit controlled by the output of the rate multiplier which constitutes the above-mentioned pulse source.
In the prior art devices, the pulse source derives the cycle-cancelling pulses from the reference frequency or from the variable frequency oscillator, typically by means of at least a programmable rate multiplier which produces a programmable number of output pulses for a fixed number of input pulses. These output pulses have an average frequency which can be any rational fraction of the frequency from which they are derived. Since they are strobed by the input pulses, however, the periods between successive output pulses will frequently vary due to the missing pulses and these variations (referred to as "jitter") will produce variations in the output frequency unless a compensation circuit is provided to reduce the effects of the jitter.
In the frequency synthesizer described in the above-mentioned mentioned U.K. Patent Specification No. 1,447,418, the frequency reduction is partly effected by a successive addition rate multiplier which, for each input pulse thereto, adds a programmable increment to an accumulated value and gives an output pulse each time the capacity of the accumulator is exceeded, leaving the excess as a residue in the accumulator. The principle of its operation can readily be appreciated by taking a simple example in which the capacity of the accumulator is unity and each input pulse adds 0.7 to the value in the accumulator. Thus the accumulator overflows and gives an output pulse for the 2nd, 3rd, 5th, 6th, 8th, 9th and 10th input pulses--i.e. seven output pulses for ten input pulses. In other words, the average pulse repetition rate has been multiplied by 0.7 by the rate multiplier. The patent specification describes a phase lock loop system in which the residue in the accumulator is converted to analog form in a digital-to-analog converter and the resultant analog signal is used to compensate for any variation in the output of a phase comparator, in the phase lock loop, due to jitter.
If there is any residual imbalance in the jitter compensation arrangement, this imbalance appears in the output frequency as a spurious discrete sideband signal. This signal may typically be 30 dB down with respect to the main output signal and, while this is adequate in the audio pass band in communication receivers, it is not adequate for broadcast receivers. If, for example, the output frequency is 100 kHz and the offset frequency is 12.5 kHz, any spurious signal would be in the adjacent channel, whereas the specification for such equipment requires the level of any such signal to be at least 90 dB down. One object of the invention is at least to mitigate this problem.
In known frequency synthesizers, the compensation signal, which effectively predicts any jitter, is derived from the circuitry of, or associated with, the rate multiplier, or at least depends upon the "history" of the pulses which cause the cycle cancellation, in order to provide the predictive compensation signal. The relevant circuitry involved is fairly complex. A further object of the invention is to provide a frequency synthesizer of the type defined in the opening paragraph hereof which enables the electronic hardware to be reduced, provides improved sideband suppression, and enables any pulse source to be used.
The above-mentioned U.K. Patent Specification No. 2,068,185A describes a frequency synthesizer of the type including a feedback system which includes a detector arranged to detect any residual jitter in the circuit after application of the compensation signal, and a variable gain amplifier arranged to control the amplitude of the compensation signal, the gain of the amplifier being controlled by the detector to reduce any said residual jitter. In this manner, the detector and amplifier from part of a feedback loop which adjusts the amplitude of the compensation signal in dependence upon the detected residual jitter in order to minimize that jitter.
The frequency synthesizer described in the above-mentioned U.K. Patent Specification No. 2,068,185A employs such a feedback system. However after a frequency step change in which the offset frequency step size is a small fraction of the main step size, the system may take some time to settle. This time, although adequate for may purposes, may be too long for the frequency synthesizer to be used, for example, in frequency-hopping radio systems or as a microwave synthesizer. The reason for this delay in the settling time can be explained by taking the example referred to above in which the main step size is 1 kHz and the offset frequency is adjustable in 10 Hz steps. The fractional step is thus 0.01 and the system receives information at the 10 Hz rate; that is to say that in the worst case the system may have to wait for the one-tenth of a second before it senses whether or not the system has any residual imbalance. For this reason it is necessary to include a time constant of this order in the feedback loop to ensure satisfactory operation under the worst case conditions where the offset frequency is 10 Hz or 990 Hz. Yet a further object of the invention is to enable this time constant to be substantially reduced in frequency synthesizers provided with a feedback control loop.